1. Field of the Invention
The present invention relates to an information processing apparatus, an information processing method, a recording medium and a program, and, more particularly, relates to an information processing apparatus and an information processing method, which carry out an arbitration for efficient acquisition of a bus by a plurality of modules when the plurality of modules carry out process using a single bus.
2. Related Art
Nowadays, electronic apparatuses and devices that are controlled by LSI's (Large Scale Integration) circuits have become popular.
In LSI's, various processes are carried out by modules (engines) including a plurality of IC's (Integrated Circuits). In such case, in order to have the process of each module of the LSI to be executed, it is required to store data in an external memory according to the process being performed, or to conveniently read out the stored data.
For this reason, the order of acquisition of a bus connected to the external memory for each module is arbitrated, in other words, a function is provided for controlling bus arbitration so that the bus acquisition is controlled for each module.
Available methods for bus arbitration include a round-robin method, a fixed priority method (a fixed priority rank method) and the like.
The round-robin method is a method in which the bus is uniformly acquired by a plurality of modules, i.e., it is a method of controlling by making the plurality of modules acquire the bus in sequence.
FIG. 1A and FIG. 1B show an example of a timing chart in which the timings when two modules of a first module and a second module acquire one bus are controlled in accordance with a round-robin method.
Here, FIG. 1A shows the timing when the first module transmits a request signal for requesting the acquisition of the bus and the timing when the bus is acquired to then execute a first process, and FIG. 1B shows the timing when the second module transmits the request signal for requesting the acquisition of the bus and the timing when the bus is acquired to then execute a second process.
The first module transmits a request signal R1 for requesting the acquisition of the bus at a time t1, and when acquiring the bus between the times t1 and t2, executes a first process 1 (in FIG. 1A, it is indicated by the encircled numeral “1”, and hereafter, an encircled numeral indicates a process in the drawing), and then transmits a request signal R2 at a time t2 of a timing when the process is ended. At this event, the round-robin method carries out the control so that the first module and the second module alternately acquire the bus. Thus, until the second module completes a second process 11, the first module cannot acquire the bus. So, a next first process 2 is not executed, staying in a standby mode.
Here, at a time t3, the second module transmits a request signal R11 and at that timing, the second module acquires the bus, and executes the second process 11 between the times t3 and t4.
At the time t4 when this second process 11 is ended, the first module can acquire the bus, thus executing the first process 2 between the times t4 and t5, and further transmitting a request signal R3 for requesting the acquisition of the bus at the time t5 when the first process 2 is ended.
Also at this time, in the round-robin method, the first module cannot acquire the bus until the completion of the process of the second module.
Under this condition, at a time t6, the second module can acquire the bus at that timing, if transmitting a request signal R12 for the bus acquisition, thus, executing a second process 12 between the times t6 and t7.
At the time t7 when this process 12 is ended, the first module can acquire the bus, thus executing a first process 3 between the times t7 and t8, and further transmitting a request signal R4 for requesting the acquisition of the bus at a time t8.
Also at that time, in the round-robin method, the first module cannot acquire the bus until the completion of the process of the second module.
Under this condition, at a time t9, the second module, if transmitting a request signal R13 for the bus acquisition, can acquire the bus at that timing, thus executing a second process 13 between the times t9 and t10 and further transmitting a request signal R14 for requesting the acquisition of the bus at that timing. At this time, in the round-robin method, the second module cannot acquire the bus until the completion of the process of the first module.
On the other hand, at the time t10 that is the timing when this second process 13 is executed, the first module can acquire the bus, thus executing a first process 4 between the times t10 and t11. At this time, the request for the bus acquisition is not transmitted.
At the time t11 when this first process 4 is ended, the second module can acquire the bus, thus executing a second process 14 between the times t11 and t12 and further transmitting a request signal R15 for requesting the bus acquisition at the time t12. Also at this time, in the round-robin method, the second module cannot acquire the bus until the completion of the process of the first module.
Under this condition, at a time t13, the first module, if transmitting a request signal R5 for requesting the bus acquisition, can acquire the bus at that timing, thus executing a first process 5 between the times t13 and t14.
At the time t14 when this first process 5 is ended, the second module can acquire the bus, thus executing a second process 15 between the times t14 and t15 and further transmitting a request signal R16 for requesting the bus acquisition at the time t15. Also at this time, in the round-robin method, the second module cannot acquire the bus until the completion of the process of the first module.
Under this condition, at a time t16, the first module, if transmitting a request signal R6 for requesting the bus acquisition, can acquire the bus at that timing, thus executing a first process 6 between the times t16 and t17.
At the time t17 when this first process 6 is ended, the second module can acquire the bus, thus executing a first process 16 between the times t17 and t18.
As mentioned above, the round-robin method is the method in which the first module and the second module alternately acquire the bus and carry out their processes.
Also, a fixed priority method (a fixed priority rank method) is a method in which if there are a plurality of modules, a priority rank is set in advance for each module, and a bus is acquired in accordance with the priority rank, if a request for requesting a bus acquisition is carried out from each module.
Also, among conventional arbitration apparatuses, there is an apparatus in which when one common resource is used between a plurality of masters, a priority rank is calculated to thereby set a grant to use the common source in accordance with the calculation result. For example, refer to Japanese Laid Open Patent Application JP-A 2002-55944 (Paragraph [0058] and FIG. 3 and FIG. 4).
By the way, as shown in FIGS. 1A, 1B as mentioned above, the frequency of accesses to an external memory of each module is typically changed on the basis of the processing conditions.
However, in FIG. 1A and FIG. 1B, for example, at the times t2, t3 and t4, the first module transmits the request signals R2, R3 and R4 for requesting the bus acquisitions. On the contrary, although the second module does not request the bus acquisition, the processes have to wait until the times t4, t7 and t10 that are the timings when the processes of the second module are ended. Also at the times t12 and t15, the second module transmits the requests R15, R16 for the bus acquisition. On the contrary, although the first module does not request the bus acquisition, the processes have to wait until the times t14 and t17 that are the timings when the processes of the first module are ended. As a result, it is not possible to attain an efficient bus arbitration process (the process for adjusting the bus acquisition), which results in the generation of unnecessary latency time. Hence, this brings about a problem that the processing speed is reduced for LSI as a whole.
Also, in the case of the fixed priority rank method, if there are many modules, a module having a higher priority rank can preferentially acquire the bus and execute the processes. However, a module having a lower priority rank cannot acquire the bus as long as the process having the higher priority rank continues to be executed. Thus, there may be a fear that a proper bus cannot be acquired when the process condition for each module is changed. This results in a problem that the processing speed is reduced.